1. Field of the Invention
The present invention relates to logic built-in self-tests, and more particularly to logic built-in self-tests including channel skipping functions.
2. Description of Background
A logic built-in self-test (LBIST) architecture used to apply patterns and observe responses on a chip is the self-test using a multiple input signature register (MISR) and a parallel shift (Stumps) register sequence generator. The basic mechanism uses a pseudo-random pattern generator (PRPG) to generate the inputs of a device's internal scan chain, initiate a functional cycle to capture the response of the device, and then compress the captured response into a MISR. The compressed response that is output from the MISR is referred to as a signature. Any corruption in the outputted signature indicates a defect in the device.
Many computer systems require scan path access for chip initialization and diagnostics. Occasionally the scan path may contain a design or manufacturing error that blocks the scan path. These errors can be difficult to debug because the scan paths are often very large and every latch in front of the blockage is not observable, and those after the blockage are not loadable. When a specific scan ring value, or channel, is required for initialization after the blockage this problem could completely disable the part.
Considering the above limitations, a method and architecture for LBIST channel skipping during functional scan operations is desired.